Bengaluru, India

Rakesh Chandrakant Pednekar

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Globalfoundries U.S. Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Rakesh Chandrakant Pednekar. Retrieved from https://idiyas.com/inventor/rakesh-chandrakant-pednekar

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Rakesh Chandrakant Pednekar and Voltage-Regulator Innovation.

Introduction

Rakesh Chandrakant Pednekar is an inventor associated with Bengaluru, India, and GlobalFoundries U.S. Inc. His patent work includes a low-dropout voltage regulator designed to reduce output-voltage ripple through coordinated feedback control.

Latest Patents

The available information identifies 1 patent for Pednekar: “Voltage regulator including a pair of feedback control loops for drive transistor control.” The invention describes an LDO circuit with a drive transistor and two concurrently operating feedback loops that adjust the transistor’s control voltage. One loop uses a comparator and a push capacitor to respond quickly, while the other uses an operational amplifier for feedback control. Together, the loops are designed to reduce ripple in the regulator’s output voltage.

Career Highlights

Pednekar’s documented patent contribution focuses on voltage regulation and circuit design. The described approach combines a faster feedback loop for initiating control adjustments with a slower loop that supports ongoing regulation.

Collaborations

Pednekar is associated with GlobalFoundries U.S. Inc. The provided information also names Siva Kumar Chinthu as a coworker, though it does not specify a direct role in this patent.

Conclusion

Rakesh Chandrakant Pednekar’s recorded patent highlights an LDO regulator design that uses paired feedback loops to improve output-voltage stability.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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