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For the Inventor, By the Inventor

Cupertino, CA, United States of America

Rajasekhar Cherabuddi

This inventor holds 25 USPTO granted patents, primarily in Database Acceleration. Top assignees: Sun Microsystems, Inc., Teradata US, Inc., Brocade Communications Systems, Inc.. Active years: 1998-2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Rajasekhar Cherabuddi. Retrieved from https://idiyas.com/inventor/rajasekhar-cherabuddi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 25

% Patents Active = 96.0

Average Co-Inventor Count = 2.2

ph-index = 12

Forward Citations = 472(Granted Patents)


Location History:

  • Sunnyvale, CA (US) (1998 - 2003)
  • Cupertino, CA (US) (2000 - 2008)
  • Saratoga, CA (US) (2013 - 2015)

Company Filing History:

goldMedal22 out of 7,642 
 
Sun Microsystems, Inc.
 patents
silverMedal2 out of 580 
 
Teradata US, Inc.
 patents
bronzeMedal1 out of 498 
 
Brocade Communications Systems, Inc.
 patents

Years Active: 1998-2015

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Areas of Expertise:
Hardware Acceleration
Database Operations
Memory Latency
Cache Optimization
Branch Prediction
Processor Architecture
Data Isolation
DMA Transfer
Speculative Execution
Multi-Processor Unit
Instruction Cache
Storage Area Network
25 patents (USPTO):Explore Patents
1. 9141670 - Methods and systems for hardware acceleration of streamed database operations and queries based on multiple hardware accelerators (2015-09-22),
2. 8468151 - Methods and systems for hardware acceleration of database operations and queries based on multiple hardware accelerators (2013-06-18),
3. 7433351 - Isolation of data, control, and management traffic in a storage area network (2008-10-07),
4. 6918071 - Yield improvement through probe-based cache size reduction (2005-07-12),
5. 6725336 - Dynamically allocated cache memory for a multi-processor unit (2004-04-20),
6. 6553435 - DMA transfer method for a system including a single-chip processor with a processing core and a device interface in different clock domains (2003-04-22),
7. 6535966 - System and method for using a page tracking buffer to reduce main memory latency in a computer system (2003-03-18),
8. 6496917 - Method to reduce memory latencies by performing two levels of speculation (2002-12-17),
9. 6477622 - Simplified writeback handling (2002-11-05),
10. 6330662 - Apparatus including a fetch unit to include branch history information to increase performance of multi-cylce pipelined branch prediction structures (2001-12-11),
11. 6289441 - Method and apparatus for performing multiple branch predictions per cycle (2001-09-11),
12. 6263416 - Method for reducing number of register file ports in a wide instruction issue processor (2001-07-17),
13. 6256729 - Method and apparatus for resolving multiple branches (2001-07-03),
14. 6256709 - Method for storing data in two-way set associative odd and even banks of a cache memory (2001-07-03),
15. 6134654 - Bi-level branch target prediction scheme with fetch address prediction (2000-10-17),

Title: The Innovative Journey of Rajasekhar Cherabuddi

Introduction: Rajasekhar Cherabuddi, a talented inventor based in Cupertino, CA, has made significant contributions to the field of technology through his innovative creations and patents.

Latest Patents: Rajasekhar Cherabuddi holds several patents in the areas of artificial intelligence, machine learning, and data analytics, showcasing his expertise in cutting-edge technologies.

Career Highlights: With a background in computer science and engineering, Rajasekhar Cherabuddi has worked for top tech companies, leading research institutions, and universities, where he has spearheaded groundbreaking projects and developments.

Collaborations: Throughout his career, Rajasekhar Cherabuddi has collaborated with renowned experts in the industry, fostering a culture of innovation and knowledge sharing to drive forward progress in the tech world.

Conclusion: Rajasekhar Cherabuddi's passion for innovation and his dedication to pushing the boundaries of technology make him a standout figure in the world of inventors, with a promising future ahead in shaping the technological landscape.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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