Bi-level branch target prediction scheme with fetch address prediction

Abstract

One embodiment of the present invention provides a system for predicting an address of an instruction following a branch instruction in a computer instruction stream. This system concurrently performs a fast single-cycle branch prediction operation to produce a first predicted address, and a more-accurate multiple-cycle branch prediction operation to produce a second predicted address. The system assumes that the first predicted address is correct and proceeds with a subsequent instruction fetch operation using the first predicted address. If the first predicted address is the same as the second predicted address, the subsequent instruction fetch operation is allowed to proceed using the first predicted address. Otherwise, the subsequent fetch operation is delayed so that it can proceed using the second predicted address. In this way, the system will typically perform a fast instruction fetch operation using the first predicted address, and will less frequently have to wait for the more-accurate second predicted address. This bi-level architecture allows branch prediction work efficiently even at the higher clock frequencies that arise as semiconductor technologies continue to improve. In accordance with one feature of the above embodiment, the multiple-cycle branch prediction operation involves selecting the second predicted address from between a branch target address, a next sequential address and a return address from a function call. In accordance with another feature, the second predicted address is selected using information from a branch type table, which contains information specifying the type of branch instructions located at particular addresses.