This inventor holds 1 USPTO granted patent. Top assignee: Intel Corporation. Active years: 2016.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2016
Title: Rainer Theur and Processor Memory Disambiguation
Introduction
Rainer Theur is an inventor based in Sehnde, Germany. His patent work includes processor architecture and techniques for managing memory operations during out-of-order execution.
Latest Patents
Theur is associated with 1 patent, titled “Instruction and Logic for Memory Disambiguation in an Out-of-Order Processor.” The invention describes a processor that combines software scheduling with hardware scheduling to reorder instructions for out-of-order execution. It uses alias information, a checking range of subsequent memory atoms, and the virtual order of instructions to assess whether software or hardware reordering has caused an error.
Career Highlights
Theur is associated with Intel Corporation. His patent reflects work on processor logic designed to evaluate memory-operation dependencies and support reliable instruction scheduling.
Collaborations
The patent information names Rakesh Ranjan and Arun Raman as Theur’s coworkers. Their shared technical context includes processor scheduling and memory disambiguation.
Conclusion
Rainer Theur’s patent contribution addresses a key challenge in processor design by helping identify errors that can arise when memory operations are reordered for execution.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile