Singapore, Singapore

Raghavendra Pai Kateel

This inventor holds 2 USPTO granted patents and 1 published patent application. Top assignee: Silicon Laboratories Inc.. Active years: 2019-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Raghavendra Pai Kateel. Retrieved from https://idiyas.com/inventor/raghavendra-pai-kateel

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 2 

% Patents Active = 100.0

Average Co-Inventor Count = 3.4

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2019-2022

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2 patents (USPTO):Explore Patents

Title: Raghavendra Pai Kateel: Innovator in Integrated Circuit Technology

Introduction

Raghavendra Pai Kateel is a notable inventor based in Singapore, SG. He has made significant contributions to the field of integrated circuit technology, holding 2 patents that showcase his innovative approach to secure systems.

Latest Patents

One of his latest patents is titled "Secure Scan Entry." This invention discloses an integrated circuit that features a secure domain. The circuitry within the integrated circuit is designed to select one of several scan modes. The sequence used for this selection also resets all flip-flops in the secure domain, ensuring that hackers cannot exploit test modes to extract data from the secure domain. The reset is generated asynchronously upon the assertion of a first signal and is terminated with a second signal, which also selects one of the scan modes. This hardware-based solution effectively prevents hacking attempts that utilize scan modes.

Another significant patent is the "Method for Detecting Faults on Retention Cell Pins." This invention includes systems and methods that pulse a clock pin of retention cells within a scan chain to shift a sequence of logic values. Successive cells are loaded with opposite logic values, and the method includes pulsing a retain pin to hold these values. The process also involves pulsing a restore pin to recover the retained logic values and comparing them with the values shifted into the scan chain to detect faults on the retain pin.

Career Highlights

Raghavendra is currently employed at Silicon Laboratories Inc., where he continues to innovate in the field of integrated circuits. His work has been instrumental in advancing secure technology solutions.

Collaborations

He collaborates with talented coworkers, including Mudit Srivastava and Shantonu Bhadury, contributing to a dynamic and innovative work environment.

Conclusion

Raghavendra Pai Kateel's contributions to integrated circuit technology through his patents reflect his commitment to innovation and security in electronic systems. His work continues to influence the industry positively.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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