The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 03, 2022

Filed:

Feb. 26, 2020
Applicant:

Silicon Laboratories Inc., Austin, TX (US);

Inventors:

Mudit Srivastava, Singapore, SG;

Raghavendra Pai Kateel, Singapore, SG;

HengWee Cheng, Singapore, SG;

Anil Shirwaikar, Austin, TX (US);

Assignee:

Silicon Laboratories Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/3177 (2006.01); G01R 31/317 (2006.01); G06F 21/74 (2013.01); G01R 31/327 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/31701 (2013.01); G06F 21/74 (2013.01);
Abstract

An integrated circuit having a secure domain is disclosed. Circuitry within the integrated circuit is used to select one of a plurality of scan modes. The sequence used to select one of the scan modes also serves to reset all of the flip-flops in the secure domain. In this way, it is impossible for a hacker to use the test modes to shift data from the secure domain out of the integrated circuit. The reset is generated asynchronously upon assertion of a first signal and is terminated upon the assertion of a second signal. The assertion of the second signal also serves to select one of the scan modes. This system cannot be hacked by any method that enters scan mode since it is a hardware based solution.


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