This inventor holds 1 USPTO granted patent. Top assignee: International Business Machines Corporation. Active years: 2012.
Company Filing History:
Years Active: 2012
Title: Raghav Kohli: Innovator in Wafer Technology
Introduction
Raghav Kohli is a notable inventor based in Essex Junction, VT (US). He has made significant contributions to the field of semiconductor technology, particularly in the area of wafer processing. His innovative approach has led to the development of a unique tool and method that enhances the efficiency of chip testing and selection.
Latest Patents
Raghav Kohli holds a patent for a "Tool and method to graphically correlate process and test data with specific chips on a wafer." This invention provides a systematic way to graphically correlate process and test data with specific chips on a multi-project wafer. The tool is designed to select certain sites and export these sites to an industry-standard map, which can be utilized in various chip picking or testing tools. The method involves importing a wafer floor plan with chips of different design parameters and manufacturing logistical information. It further includes graphically rendering each chip on the wafer to scale within a unit cell, utilizing the imported data.
Career Highlights
Raghav Kohli is currently associated with International Business Machines Corporation (IBM), where he continues to innovate and contribute to advancements in technology. His work has been instrumental in improving the processes involved in semiconductor manufacturing and testing.
Collaborations
Throughout his career, Raghav has collaborated with talented individuals such as Mark J Flemming and Alexander Joseph Franz. These collaborations have fostered an environment of innovation and creativity, leading to significant advancements in their respective fields.
Conclusion
Raghav Kohli's contributions to wafer technology exemplify the impact of innovative thinking in the semiconductor industry. His patent and ongoing work at IBM highlight his commitment to enhancing the efficiency of chip testing and selection processes.
