The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2012
Filed:
Jan. 14, 2008
Mark J. Flemming, Essex Junction, VT (US);
Alexander J. Franz, Westford, VT (US);
Tyler D. Kieft, Essex Junction, VT (US);
Raghav Kohli, Essex Junction, VT (US);
Karl V. Swanke, Essex Junction, VT (US);
Matthew S. Turnbull, Essex Junction, VT (US);
Matthew Walker, South Burlington, VT (US);
Mark J. Flemming, Essex Junction, VT (US);
Alexander J. Franz, Westford, VT (US);
Tyler D. Kieft, Essex Junction, VT (US);
Raghav Kohli, Essex Junction, VT (US);
Karl V. Swanke, Essex Junction, VT (US);
Matthew S. Turnbull, Essex Junction, VT (US);
Matthew Walker, South Burlington, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A tool and method is provided to graphically correlate process and test data with specific chips on a multi-project wafer. The tool and method is configured and implemented to select certain sites and export these sites to an industry standard map that can be used in a variety of chip picking or test tools. In one embodiment, the method includes importing a wafer floor plan with chips of different design parameters and importing manufacturing logistical information of the chips. The method further includes graphically rendering each chip on the wafer to scale within a unit cell using the imported wafer floor plan and the manufacturing logistical information.