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For the Inventor, By the Inventor

Portland, OR, United States of America

Priyadarsan Patra

This inventor holds 5 USPTO granted patents. Top assignee: Intel Corporation. Active years: 2003-2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Priyadarsan Patra. Retrieved from https://idiyas.com/inventor/priyadarsan-patra

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 5

% Patents Active = 80.0

Average Co-Inventor Count = 1.7

ph-index = 4

Forward Citations = 49(Granted Patents)


Location History:

  • Portland, OR (US) (2003 - 2011)
  • Austin, TX (US) (2019)

Company Filing History:

goldMedal5 out of 56,365 
 
Intel Corporation
 patents

Years Active: 2003-2019

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5 patents (USPTO):Explore Patents
1. 10198333 - Test, validation, and debug architecture (2019-02-05),
2. 8055697 - Method and device for dynamically verifying a processor architecture (2011-11-08),
3. 6721924 - Noise and power optimization in high performance circuits (2004-04-13),
4. 6556962 - Method for reducing network costs and its application to domino circuits (2003-04-29),
5. 6529861 - Power consumption reduction for domino circuits (2003-03-04),

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Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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