Vancouver, Canada

Pratyush Chandrapati

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Intel Ndtm US LLC. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Pratyush Chandrapati. Retrieved from https://idiyas.com/inventor/pratyush-chandrapati-e3j8aqxl

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

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Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Pratyush Chandrapati: Innovator in NAND Memory Technology

Introduction

Pratyush Chandrapati is a notable inventor based in Vancouver, Canada. He has made significant contributions to the field of memory technology, particularly in NAND memory arrays. His innovative work focuses on enhancing power efficiency in memory systems.

Latest Patents

Chandrapati holds a patent for a technology titled "Power efficient array discharge for program boosting." This invention provides systems, apparatuses, and methods that issue a program pulse to a selected subblock of a NAND memory array. It also conducts a pulse recovery phase after the program pulse and shuts down unselected subblocks in the NAND memory array during the pulse recovery phase. This advancement aims to improve the overall efficiency of NAND memory operations.

Career Highlights

Pratyush Chandrapati is currently employed at Intel NDTM US LLC, where he continues to develop innovative solutions in memory technology. His work at Intel has positioned him as a key player in the advancement of NAND memory systems.

Collaborations

Chandrapati collaborates with Tarek Ameen, contributing to the development of cutting-edge technologies in their field.

Conclusion

Pratyush Chandrapati's contributions to NAND memory technology exemplify the impact of innovative thinking in the tech industry. His patent on power-efficient systems showcases his commitment to enhancing memory performance and efficiency.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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