Hsinchu, Taiwan

PO-Yang Chen

This inventor holds 1 USPTO granted patent. Top assignee: Powerchip Semiconductor Manufacturing Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: PO-Yang Chen. Retrieved from https://idiyas.com/inventor/po-yang-chen-pm8za87t

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: PO-Yang Chen and Wafer Optical Inspection

Introduction

PO-Yang Chen is an inventor based in Hsinchu, Taiwan. His work includes a patent for a system designed to inspect wafers optically and determine their number and positions within a batch.

Latest Patents

Chen is associated with 1 patent, titled “Wafer Optical Inspection System and Inspection Method.” The system uses an image-capturing device with a photosensitive device, an LED source, and a laser source. The LED creates a reflective feature at the edges of a batch of wafers, while the laser creates a contour feature. The photosensitive device captures these features alongside the wafer image to form a side image of the wafer group. An image-recognition device then uses that image to identify the number and positions of the wafers in the batch.

Career Highlights

Chen works at Powerchip Semiconductor Manufacturing Corporation. His patented inspection approach combines optical imaging and image recognition to support wafer identification and positioning.

Collaborations

Chen’s listed coworkers include Ke-Fen Chen and Yu-Chih Lin. The available information identifies them as coworkers but does not specify their roles in the patent.

Conclusion

PO-Yang Chen’s patent describes an optical inspection system that uses reflective and contour features to identify wafers and their positions, reflecting his work in semiconductor manufacturing technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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