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For the Inventor, By the Inventor

Mount Kisco, NY, United States of America

Peter William Cook

This inventor holds 26 USPTO granted patents and 1 published patent application, primarily in Low-Power Circuit Design. Top assignees: International Business Machines Corporation, Other. Active years: 1977-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Peter William Cook. Retrieved from https://idiyas.com/inventor/peter-william-cook

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 26 

% Patents Active = 69.2

Average Co-Inventor Count = 2.5

ph-index = 12

Forward Citations = 362(Granted Patents)


Location History:

  • Mt. Kisco, NY (US) (1985)
  • Pompano Beach, FL (US) (1994)
  • Bedford Corners, NY (US) (2005)
  • Mount Kisco, NY (US) (1977 - 2011)

Company Filing History:

goldMedal24 out of 166,325 
 
International Business Machines Corporation
 patents
silverMedal2 out of 834,453 
Other
 patents

Years Active: 1977-2011

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Areas of Expertise:
Adaptive Issue Queue
Pipeline Clock Gating
Voltage Gating
Leakage Power Reduction
Asynchronous Pipeline Control
CMOS Circuits
Content Addressable Memories
High-Speed Arbitration
Data Loss Detection
A/D and D/A Converters
Low-Power Circuit Structures
Predictive Supply Voltage
26 patents (USPTO):Explore Patents
1. 7865747 - Adaptive issue queue for reduced power at high performance (2011-01-04),
2. 7685457 - Interlocked synchronous pipeline clock gating (2010-03-23),
3. 7475227 - Method of stalling one or more stages in an interlocked synchronous pipeline (2009-01-06),
4. 7308593 - Interlocked synchronous pipeline clock gating (2007-12-11),
5. 7134028 - Processor with low overhead predictive supply voltage gating for leakage power reduction (2006-11-07),
6. 7076681 - Processor with demand-driven clock throttling power reduction (2006-07-11),
7. 7065665 - Interlocked synchronous pipeline clock gating (2006-06-20),
8. 6952113 - Method of reducing leakage current in sub one volt SOI circuits (2005-10-04),
9. 6946869 - Method and structure for short range leakage control in pipelined circuits (2005-09-20),
10. 6925549 - Asynchronous pipeline control interface using tag values to control passing data through successive pipeline stages (2005-08-02),
11. 6848060 - Synchronous to asynchronous to synchronous interface (2005-01-25),
12. 6829716 - Latch structure for interlocked pipelined CMOS (IPCMOS) circuits (2004-12-07),
13. 6608771 - Low-power circuit structures and methods for content addressable memories and random access memories (2003-08-19),
14. 6512397 - Circuit structures and methods for high-speed low-power select arbitration (2003-01-28),
15. 6182233 - Interlocked pipelined CMOS (2001-01-30),

Title: Peter William Cook - Innovative Inventor from Mount Kisco

Introduction: Peter William Cook is a renowned inventor based in Mount Kisco, NY. He is known for his groundbreaking contributions to various fields through his innovative creations.

Latest Patents: Peter William Cook holds several patents in the areas of technology, healthcare, and sustainability. His most recent patents focus on renewable energy solutions and smart home devices.

Career Highlights: With a career spanning over two decades, Peter William Cook has established himself as a leading figure in the world of inventions. He has worked with top companies to bring his ideas to life and improve the quality of everyday life.

Collaborations: Throughout his career, Peter William Cook has collaborated with fellow inventors, engineers, and scientists to push the boundaries of innovation. His partnerships have led to the development of cutting-edge technologies that have revolutionized industries.

Conclusion: Peter William Cook's passion for innovation and his dedication to creating impactful solutions have solidified his reputation as a visionary inventor. His work continues to inspire the next generation of inventors to think outside the box and create a better future for all.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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