Santa Clara, CA, United States of America

Perrine Peresse

This inventor holds 1 USPTO granted patent. Top assignee: Sifive, Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Perrine Peresse. Retrieved from https://idiyas.com/inventor/perrine-peresse-89ker7zv

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Perrine Peresse: Patent Inventor in Santa Clara

Introduction

Perrine Peresse is an inventor based in Santa Clara, California. Her work includes a patent related to page table entry caches and multiple tag lengths.

Latest Patents

Peresse is associated with one patent, titled “Page Table Entry Caches with Multiple Tag Lengths.” The invention concerns cache designs for page table entries that use tags of varying lengths.

Career Highlights

Peresse is associated with SiFive, Inc., a company working in the semiconductor and computing technology sector. Her patent reflects work on computer architecture and memory-management technologies.

Collaborations

Peresse is listed alongside fellow inventor Shubhendu Sekhar Mukherjee on the patent. Their collaboration is credited with the invention described in the patent record.

Conclusion

Perrine Peresse’s patent on page table entry caches with multiple tag lengths highlights her contribution to computer architecture innovation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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