Pawana Shrestha

Title: Pawana Shrestha: Innovator in N-polar GaN MISHEMTs Technology

Introduction

Pawana Shrestha is a notable inventor based in Goleta, California. He has made significant contributions to the field of semiconductor technology, particularly in the development of N-polar GaN MISHEMTs. His innovative approach addresses critical challenges in linearity control for high-frequency applications.

Latest Patents

Pawana Shrestha holds a patent titled "Approach to controlling linearity in N-polar GaN MISHEMTs." This invention utilizes derivative cancellation techniques to linearize transistors using a single device structure. The patent describes a unique N-polar transistor structure that includes a channel, a cap structure with multiple layers, and source and drain contacts. The design allows for the formation of at least two different threshold voltages, enabling current to combine in the ohmic region with minimal parasitic inductance.

Career Highlights

Pawana Shrestha is affiliated with the University of California, where he continues to advance research in semiconductor technologies. His work has garnered attention for its potential applications in high-frequency electronics, particularly in the mm-wave regime.

Collaborations

Pawana has collaborated with Brian Romanczyk, contributing to the development of innovative solutions in the field of semiconductor devices.

Conclusion

Pawana Shrestha's contributions to N-polar GaN MISHEMTs technology exemplify the importance of innovation in advancing semiconductor applications. His work continues to influence the field and pave the way for future advancements.