New Delhi, India

Pankaj Kumar Dwivedi

This inventor holds 2 USPTO granted patents. Top assignee: Mentor Graphics Corporation. Active years: 2015-2020.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Pankaj Kumar Dwivedi. Retrieved from https://idiyas.com/inventor/pankaj-kumar-dwivedi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 2.7

ph-index = 1

Forward Citations = 3(Granted Patents)


Location History:

  • Varanasi, IN (2015)
  • New Delhi, IN (2020)

Company Filing History:


Years Active: 2015-2020

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2 patents (USPTO):Explore Patents

Title: Pankaj Kumar Dwivedi: Innovator in Design Verification Tools

Introduction

Pankaj Kumar Dwivedi is a notable inventor based in New Delhi, India. He has made significant contributions to the field of design verification, particularly in the context of electronic design automation. With a total of 2 patents, his work focuses on enhancing the operational capabilities of electronic systems.

Latest Patents

One of his latest patents is titled "Power mode-based operational capability-aware code coverage." This application discloses a design verification tool that implements a functional verification environment with a computing system, a hardware emulator, or a combination thereof. The design verification tool can identify operational states of circuitry described in the circuit design from a power intent specification. It generates code coverage bins based on these operational states, which correspond to the operational capabilities of the circuitry supported by each of the power modes. The tool records code coverage events during functional verification operations and generates coverage metrics based on these records.

Another significant patent is "Hierarchical finite state machine generation for power state behavior in an electronic design." This invention provides techniques and apparatuses for generating a hierarchical representation of the power behavior of an electronic design. In some implementations, a flat finite state machine representing the power behavior is extracted from the power specification. Subsequently, a hierarchical finite state machine representation is generated from the flat finite state machine, the power specification, and the logical specification.

Career Highlights

Pankaj Kumar Dwivedi is currently employed at Mentor Graphics Corporation, a leading company in electronic design automation. His work at Mentor Graphics has allowed him to develop innovative solutions that enhance the efficiency and effectiveness of design verification processes.

Collaborations

He has collaborated with notable coworkers such as Amit Srivastava and Shweta Gulati, contributing to various projects that advance the field of electronic design.

Conclusion

Pankaj Kumar Dwivedi's contributions to design verification tools demonstrate his commitment to innovation in electronic design automation. His patents reflect a deep understanding of the complexities involved in power state behavior and operational capabilities. His work continues to influence the industry positively.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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