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For the Inventor, By the Inventor

San Diego, CA, United States of America

Pankaj Deshmukh

This inventor holds 15 USPTO granted patents and 14 published patent applications and 1 EPO patent, primarily in Memory Systems. Top assignee: Qualcomm Incorporated. Active years: 2022-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Pankaj Deshmukh. Retrieved from https://idiyas.com/inventor/pankaj-deshmukh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 15 

% Patents Active = 86.7

 

Average Co-Inventor Count = 4.7

ph-index = 1

Forward Citations = 6(Granted Patents)


Company Filing History:

goldMedal15 out of 45,176 
 
Qualcomm Incorporated
 patents

Years Active: 2022-2026

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Areas of Expertise:
Process-In-Memory
Address Hashing
Memory Controller
Rowhammer Mitigation
Adaptive Refresh
Latency Reduction
Metadata Registers
Dynamic Access Management
Dual Ranks Memory
High Performance Memory
Memory Device
15 patents (USPTO):Explore Patents
1. 12717726 - Process-in-memory (PIM)-aware address hashing (2026-08-25),
2. 12632398 - Memory system with adaptive refresh (2026-05-19),
3. 12625611 - Metadata registers for a memory device (2026-05-12),
4. 12308069 - DRAM with quick random row refresh for rowhammer mitigation (2025-05-20),
5. 12307092 - Reducing latency in pseudo channel based memory systems (2025-05-20),
6. 12299283 - Self-characterizing, evaluating, and adaptive high performance memory controller (2025-05-13),
7. 12211543 - Dynamic rowhammer management (2025-01-28),
8. 12159033 - Metadata registers for a memory device (2024-12-03),
9. 12153531 - Multiple-core memory controller (2024-11-26),
10. 12094515 - Dynamic random access memory (DRAM) row hammering mitigation (2024-09-17),
11. 12038855 - Memory system with adaptive refresh (2024-07-16),
12. 11907141 - Flexible dual ranks memory system to boost performance (2024-02-20),
13. 11893240 - Reducing latency in pseudo channel based memory systems (2024-02-06),
14. 11881862 - Mitigation of duty-cycle distortion (2024-01-23),
15. 11360897 - Adaptive memory access management (2022-06-14),

Title: Pankaj Deshmukh: Innovator in DRAM Technology

Introduction

Pankaj Deshmukh is a prominent inventor based in San Diego, CA, known for his significant contributions to the field of memory technology. With a total of 12 patents to his name, he has made remarkable advancements that enhance the performance and efficiency of DRAM systems.

Latest Patents

One of his latest patents is titled "DRAM with quick random row refresh for rowhammer mitigation." This innovation involves a DRAM memory controller that identifies a marker command directed to a specific row in the DRAM. If a certain threshold probability is met upon identifying the marker command, the controller commands the DRAM to refresh a neighboring row, which may either be adjacent to the given row or a recently-closed row. Another notable patent is "Reducing latency in pseudo channel based memory systems." This invention includes methods and devices designed to minimize latency in pseudo channel-based memory systems. It features a first pseudo channel selection device that selectively connects one of several pseudo channels to a first input/output (IO), and a second device that does the same for a second IO. These devices can concurrently connect a first pseudo channel to both IOs, thereby improving memory access efficiency.

Career Highlights

Pankaj Deshmukh is currently employed at Qualcomm Incorporated, a leading company in wireless technology and semiconductor design. His work at Qualcomm has positioned him as a key player in the development of advanced memory solutions.

Collaborations

Throughout his career, Pankaj has collaborated with talented individuals such as Jungwon Suh and Shyamkumar Thoziyoor. These collaborations have further enriched his innovative endeavors and contributed to the success of his projects.

Conclusion

Pankaj Deshmukh's contributions to DRAM technology and memory systems have established him as a notable inventor in the field. His innovative patents reflect his commitment to enhancing memory performance and efficiency, making a significant impact on the industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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