West Linn, OR, United States of America

Omer Ghazi Samman


Average Co-Inventor Count = 8.0

ph-index = 1

Forward Citations = 24(Granted Patents)


Company Filing History:

goldMedal1 out of 832,812 
Other
 patents

Years Active: 2005

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1 patent (USPTO):Explore Patents

Title: Innovations in Integrated Circuits: The Contributions of Omer Ghazi Samman

Introduction: Omer Ghazi Samman, an innovative inventor based in West Linn, Oregon, has made significant strides in the field of integrated circuits. With one patent to his name, his work focuses on improving the efficiency of testing multiple cores embedded in these circuits.

Latest Patents: Samman's notable patent is titled "Scheduling the Concurrent Testing of Multiple Cores Embedded in an Integrated Circuit." This inventive method addresses the complexities of scheduling tests for multiple cores by formulating the problem as a bin-packing problem. Using a modified two-dimensional or three-dimensional bin-packing heuristic, the scheduling process incorporates the integrated circuit pins, core test time, and an optional peak power dimension. This holistic approach allows for a more efficient testing schedule that optimally fits core test representations into defined parameters.

Career Highlights: Samman's career reflects a dedication to advancing technology within integrated circuits. His work has not only contributed to efficiencies in testing but also demonstrated a keen understanding of the technical challenges involved in concurrent testing methods.

Collaborations: Throughout his career, Omer Ghazi Samman has collaborated with esteemed colleagues including Nilanjan Mukherjee and Chien-Chung Tsai. These collaborations have enriched his research and contributed to the collective advancement of knowledge in the field.

Conclusion: Omer Ghazi Samman's contributions to the field of integrated circuits through his patent on scheduling concurrent testing represent a valuable innovation. His efforts, alongside collaborations with other skilled individuals, are set to enhance the efficiency of testing procedures in integrated circuits, paving the way for future advancements in technology.

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