Other

Omer Ghazi Samman

Wu-Tung Cheng

Nilanjan Mukherjee

Yu Jane Huang

Paul J Reuter

Yahya M Z Mustafa

Sudhakar Mannapuram Reddy

Chien-Chung Tsai

Methods are described for scheduling the concurrent testing of multiple cores embedded in an integrated circuit. Test scheduling is performed by formulating the problem as a bin-packing problem and using a modified two-dimensional or three-dimensional bin-packing heuristic. The tests of multiple cores are represented as functions of at least the integrated circuit pins used to test the core and the core test time. The representations may include a third dimension of peak power required to test the core. The test schedule is represented as a bin having dimensions of at least integrated circuit pins and integrated circuit test time. The bin may include a third dimension of peak power. The scheduling of the multiple cores is accomplished by fitting the multiple core test representations into the bin.

Scheduling the concurrent testing of multiple cores embedded in an integrated circuit

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West Linn, OR, United States of America

Omer Ghazi Samman