The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 23, 2005
Filed:
Jul. 31, 2002
Nilanjan Mukherjee, Wilsonville, OR (US);
Chien-chung Tsai, Tualatin, OR (US);
Wu-tung Cheng, Lake Oswego, OR (US);
Omer Ghazi Samman, West Linn, OR (US);
Yahya M. Z. Mustafa, Wilsonville, OR (US);
Paul J. Reuter, Northboro, MA (US);
Yu Huang, Marlborough, MA (US);
Sudhakar Mannapuram Reddy, Iowa City, IA (US);
Nilanjan Mukherjee, Wilsonville, OR (US);
Chien-Chung Tsai, Tualatin, OR (US);
Wu-Tung Cheng, Lake Oswego, OR (US);
Omer Ghazi Samman, West Linn, OR (US);
Yahya M. Z. Mustafa, Wilsonville, OR (US);
Paul J. Reuter, Northboro, MA (US);
Yu Huang, Marlborough, MA (US);
Sudhakar Mannapuram Reddy, Iowa City, IA (US);
Other;
Abstract
Methods are described for scheduling the concurrent testing of multiple cores embedded in an integrated circuit. Test scheduling is performed by formulating the problem as a bin-packing problem and using a modified two-dimensional or three-dimensional bin-packing heuristic. The tests of multiple cores are represented as functions of at least the integrated circuit pins used to test the core and the core test time. The representations may include a third dimension of peak power required to test the core. The test schedule is represented as a bin having dimensions of at least integrated circuit pins and integrated circuit test time. The bin may include a third dimension of peak power. The scheduling of the multiple cores is accomplished by fitting the multiple core test representations into the bin.