Santa Clara, CA, United States of America

Nuwan S Dodampegamage

This inventor holds 1 USPTO granted patent. Top assignee: Applied Materials, Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Nuwan S Dodampegamage. Retrieved from https://idiyas.com/inventor/nuwan-s-dodampegamage

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Average Co-Inventor Count = 1.0

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Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Nuwan S. Dodampegamage: Semiconductor Processing Innovation

Introduction

Nuwan S. Dodampegamage is an inventor based in Santa Clara, California, and is associated with Applied Materials, Inc. His patent work addresses a challenge in semiconductor processing: reducing electrical arcing involving an electrostatic chuck.

Latest Patents

Dodampegamage is named on one patent, titled “Arc Current Reduction from an Electrostatic Chuck.” The invention concerns a semiconductor processing chamber with an electrostatic chuck (ESC) that supports a substrate during processing. An ESC power source supplies chucking voltage to one or more electrodes and uses an adjustable current limit selected according to characteristics of the process. By preventing the supplied current from exceeding that limit, the system is designed to reduce the risk of current arcs discharging into the substrate.

Career Highlights

Dodampegamage’s listed patent reflects work in semiconductor equipment and process control. His association with Applied Materials, Inc. connects his inventive work to a company that develops equipment and technologies for semiconductor manufacturing.

Collaborations

The available information identifies Applied Materials, Inc. as Dodampegamage’s company affiliation and lists the patent’s technical focus. It does not specify additional co-inventors or collaborators.

Conclusion

Nuwan S. Dodampegamage’s patent on adjustable current limiting for electrostatic chucks presents an approach to reducing arcing risks during semiconductor processing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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