This inventor holds 1 USPTO granted patent. Top assignee: Stmicroelectronics S.r.l.. Active years: 2011.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 2011
Title: Nunzia Malagnino: Innovator in Vertical Interconnections
Introduction
Nunzia Malagnino is a notable inventor based in Torre Annunziata, Italy. She has made significant contributions to the field of integrated circuits, particularly in the area of vertical interconnections. Her innovative approach has led to the development of a unique method that enhances the fabrication process of these essential components.
Latest Patents
Nunzia holds a patent for a "Low cost method of fabrication of vertical interconnections combined to metal top electrodes." This method involves forming a vertical interconnection through a dielectric layer between upper and lower electrically conductive layers of an integrated circuit. The process includes creating an opening through the dielectric layer and utilizing a printing technique to place a solidifiable electrically conductive filler into the opening. Once solidified, this filler forms a solidified electrically conducting connection, which is then covered by a metallization layer to complete the vertical interconnection.
Career Highlights
Nunzia is currently employed at STMicroelectronics S.r.l., where she continues to push the boundaries of innovation in semiconductor technology. Her work has been instrumental in improving the efficiency and cost-effectiveness of integrated circuit manufacturing.
Collaborations
Throughout her career, Nunzia has collaborated with talented professionals, including Rossana Scaldaferri and Luigi Giuseppe Occhipinti. These partnerships have fostered a creative environment that encourages the exchange of ideas and advancements in technology.
Conclusion
Nunzia Malagnino's contributions to the field of integrated circuits exemplify her dedication to innovation and excellence. Her patented method for vertical interconnections represents a significant advancement in semiconductor technology.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
