Higashihiroshima, Japan

Norio Sadachika

This inventor holds 2 USPTO granted patents. Top assignees: Hiroshima University, Semiconductor Technology Academic Research Center. Active years: 2011-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Norio Sadachika. Retrieved from https://idiyas.com/inventor/norio-sadachika

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 50.0

Average Co-Inventor Count = 5.3

ph-index = 1

Forward Citations = 5(Granted Patents)


Company Filing History:


Years Active: 2011-2014

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2 patents (USPTO):Explore Patents

Title: Norio Sadachika: Innovator in Circuit Simulation Technologies

Introduction

Norio Sadachika is a prominent inventor based in Higashihiroshima, Japan. He has made significant contributions to the field of semiconductor technology, particularly in circuit simulation and device modeling. With a total of 2 patents, his work has advanced the understanding and functionality of MOSFETs and LDMOSFETs.

Latest Patents

One of Sadachika's latest patents is focused on the circuit simulation of MOSFETs. This innovative arithmetic device calculates the surface potential of a silicon layer by performing computations based on a mathematical expression and device parameters stored in a storage device. It also calculates the surface potential of a bulk layer under a buried oxide film when the silicon layer is in both partially and fully depleted states. The device then performs iterative calculations to obtain the surface potential of the bulk layer and subsequently calculates the lower surface potential of the silicon layer.

Another significant patent involves a simulation method and apparatus for LDMOSFETs. In this invention, the drift region, which increases the breakdown voltage in an LDMOSFET, is treated as a resistive element. The potential distribution of the overall device is calculated by considering resistance through iterative calculations. Additionally, capacitance generated in the drift region is analytically calculated, assuming a linear potential distribution, while capacitance in the overlap region between the gate electrode and the drift region is calculated by considering the potential from the depletion region to the accumulation region.

Career Highlights

Norio Sadachika has worked with notable institutions such as the Semiconductor Technology Academic Research Center and Hiroshima University. His experience in these organizations has allowed him to collaborate with other experts in the field and contribute to groundbreaking research.

Collaborations

Some of his notable coworkers include Mitiko Miura and Masahiro Yokomichi. Their collaborative efforts have further enriched the research and development in semiconductor technologies.

Conclusion

Norio Sadachika's contributions to circuit simulation and semiconductor technology have established him as a key figure in the field. His innovative patents and collaborations continue to influence advancements in electronic devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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