Fukui, Japan

Norimasa Yafune

This inventor holds 2 USPTO granted patents. Top assignee: Sharp Kabushiki Kaisha Corporation. Active years: 2010-2011.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Norimasa Yafune. Retrieved from https://idiyas.com/inventor/norimasa-yafune

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 50.0

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 5(Granted Patents)


Location History:

  • Nara, JP (2010)
  • Fukui, JP (2011)

Company Filing History:


Years Active: 2010-2011

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2 patents (USPTO):Explore Patents

Title: Norimasa Yafune: Innovator in Semiconductor Technology

Introduction

Norimasa Yafune is a prominent inventor based in Fukui, Japan. He has made significant contributions to the field of semiconductor technology, holding 2 patents that showcase his innovative approach to electronic components.

Latest Patents

One of Yafune's latest patents is for a field effect transistor. This invention includes a GaN epitaxial substrate, a gate electrode formed on an electron channel layer of the substrate, and source and drain electrodes arranged spaced apart by a prescribed distance on opposite sides of the gate electrode. The source and drain electrodes are in ohmic contact with the substrate. At the upper portion of the gate electrode, a field plate is formed protruding like a visor to the side of the drain electrode. Between the electron channel layer of the epitaxial substrate and the field plate, a dielectric film is formed. The dielectric film is partially removed at a region immediately below the field plate, to be flush with a terminal end surface of the field plate. The dielectric film extends from a lower end of the removed portion to the drain electrode, to be overlapped on the drain electrode.

Another notable patent is for a semiconductor switching element and semiconductor circuit apparatus. In this invention, a semiconductor layer is formed on a substrate, or on a semiconductor substrate, where a source electrode and a drain electrode are disposed at a predetermined interval in a direction along the surface of the substrate. A second gate electrode is provided between the source electrode and the drain electrode, which is electrically connected with the source electrode and structured with two types of electrode material layers having Schottky barriers of different heights from each other.

Career Highlights

Norimasa Yafune is associated with Sharp Kabushiki Kaisha Corporation, where he continues to develop innovative semiconductor technologies. His work has significantly impacted the efficiency and performance of electronic devices.

Collaborations

Yafune collaborates with John Kevin Twynam, contributing to advancements in semiconductor technology through their combined expertise.

Conclusion

Norimasa Yafune's contributions to semiconductor technology through his patents and collaborations highlight his role as an influential inventor in the field. His innovative designs continue to shape the future of electronic components.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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