Norihito Nakamoto

Title: Norihito Nakamoto: Innovator in Library Cell Optimization

Introduction

Norihito Nakamoto is a notable inventor based in Clifton Park, NY (US). He has made significant contributions to the field of semiconductor design, particularly in optimizing library cells with wiring in metallization layers. His innovative approach addresses design rule violations, enhancing the efficiency of integrated circuits.

Latest Patents

Nakamoto holds a patent for "Optimizing library cells with wiring in metallization layers." This patent focuses on identifying original cell design rule violations concerning a second wiring layer while maintaining the conductors in their original positions. The process involves offsetting the conductors into different positions and repeating the identification of violations for each offset. Metrics are generated for both the original cell and each offset position. The original cell or the pitch of the second wiring layer can then be altered to produce modifications. This iterative process ensures that the cell selected produces the lowest number of design rule violations.

Career Highlights

Nakamoto is currently employed at GlobalFoundries Inc., a leading semiconductor manufacturer. His work has been instrumental in advancing the design and functionality of integrated circuits, making him a valuable asset to his team and the industry.

Collaborations

Nakamoto collaborates with talented professionals such as Gregory Allen Northrop and Lionel Riviere-Cazaux. Their combined expertise contributes to the innovative projects at GlobalFoundries Inc.

Conclusion

Norihito Nakamoto's contributions to library cell optimization demonstrate his commitment to advancing semiconductor technology. His innovative patent and collaborative efforts highlight his role as a key figure in the field.