Fuchu, Japan

Noboru Yokoya

This inventor holds 2 USPTO granted patents. Top assignee: Kabushiki Kaisha Toshiba. Active years: 1999-2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Noboru Yokoya. Retrieved from https://idiyas.com/inventor/noboru-yokoya-td4qi48o

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 1.8

ph-index = 2

Forward Citations = 4(Granted Patents)


Location History:

  • Yokohama, JP (1999)
  • Fuchu, JP (2006)

Company Filing History:


Years Active: 1999-2006

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2 patents (USPTO):Explore Patents

Title: The Innovative Mind of Noboru Yokoya

Introduction

Noboru Yokoya is a talented inventor based in Fuchu, Japan. He has made significant contributions to the field of semiconductor manufacturing, holding a total of two patents. His work focuses on design systems that enhance the efficiency and accuracy of semiconductor devices.

Latest Patents

Noboru Yokoya's recent patent, titled "Design System of Alignment Marks for Semiconductor Manufacture," presents a comprehensive solution for the creation of alignment marks used in semiconductor device manufacturing. This innovative design system incorporates a memory that stores both mark and process data. It features a first process simulator that evaluates the substrate structure before the patterning phase based on the gathered process data. Additionally, a second process simulator predicts the processed shape of the alignment mark after it's patterning, while a signal waveform simulator analyzes the detection signal waveform obtained from the processed shape. Finally, a signal evaluation device assesses the mark's suitability for the manufacturing process, ensuring improved reliability and precision.

Another noteworthy patent from Yokoya is "Semiconductor Device and Method for Manufacturing the Same." This patent addresses the mask pattern applied to the peripheral portion of a wafer, maintaining an open/close ratio similar to that of the central part. The method adheres to a looser design rule, which allows for enhanced latitude during out-of-focus exposure while preventing process accuracy variance due to micro-loading effects. This innovative solution contributes to more robust semiconductor manufacturing practices.

Career Highlights

Noboru Yokoya currently works for Toshiba Corporation, a leading company in the field of technology and semiconductor manufacturing. His expertise in designing efficient manufacturing processes makes him a valuable asset to the organization. Notably, he collaborates closely with Takuya Kouno, another skilled professional in the industry.

Collaborations

Working alongside Takuya Kouno, Noboru Yokoya fosters a teamwork-oriented environment that significantly contributes to advancements in semiconductor technologies. Their combined efforts lead to innovative solutions that enhance manufacturing efficiency.

Conclusion

Noboru Yokoya's dedication to semiconductor innovation is evident through his impactful patents and professional collaborations. His work is paving the way for advancements in semiconductor manufacturing processes, showcasing the importance of innovation in this critical field. With his contributions, the future of semiconductor technology looks promising.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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