Kabushiki Kaisha Toshiba

Noboru Yokoya

Takashi Sato

Takashi Sakamoto

Tatsuhiko Higashiki

Ichiro Mori

Yoshiyuki Shioyama

Takuya Kouno

A design system of an alignment mark for manufacturing a semiconductor device includes a memory which stores at least mark data including pattern information regarding plural kinds of marks and process data including condition information of manufacturing processes, and a first process simulator which simulates a substrate structure before patterning based on the process data, the substrate structure being formed in an identified manufacturing process. Moreover, the design system includes a second process simulator which simulates a processed shape of an identified mark after the patterning based on the simulated substrate structure and the process data, the mark formed in the manufacturing process, a signal waveform simulator which simulates a detection signal waveform of the mark, the waveform being obtained from the simulated processed shape of the mark, and a signal evaluation device which evaluates a suitability of the mark for the identified manufacturing process based on the simulated detection signal waveform.

Design system of alignment marks for semiconductor manufacture

A mask pattern applied to a peripheral portion of a wafer has an open/close ratio substantially the same as that in a central portion thereof and prepared according to a looser design rule than that for forming the central portion. The looser design rule has a high latitude for out-of-focus exposure and provides high resistance to pattern removal. Since the open/close ratios in the central portion and the peripheral portion of the wafer are substantially the same, variance in process accuracy due to a micro-loading effect can be prevented.

Semiconductor device and method for manufacturing the same

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Fuchu, Japan

Noboru Yokoya