Kessel-lo, Belgium

Nikolaos Minas

This inventor holds 2 USPTO granted patents. Top assignee: Imec Vzw. Active years: 2013-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Nikolaos Minas. Retrieved from https://idiyas.com/inventor/nikolaos-minas

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 2.7

ph-index = 2

Forward Citations = 16(Granted Patents)


Company Filing History:


Years Active: 2013-2014

Loading Chart...
2 patents (USPTO):Explore Patents

Title: The Innovative Contributions of Nikolaos Minas

Introduction

Nikolaos Minas is a prominent inventor based in Kessel-lo, Belgium. He has made significant contributions to the field of integrated circuits, particularly in the testing of through-silicon vias (TSVs). With a total of 2 patents, his work has advanced the understanding and functionality of 3D chip stacks.

Latest Patents

Nikolaos Minas holds two notable patents. The first patent is titled "On-chip testing using time-to-digital conversion." This invention discloses a method and system for testing the functionality of a TSV in an integrated circuit. The functionality is tested by measuring its capacitance from one side only. The capacitance of the TSV can be determined by measuring a timing delay introduced in a measurement circuit due to the presence of the TSV. The timing delay is determined by comparing the timing of a measurement signal from the measurement circuit with the timing of a reference signal provided by a reference circuit. This comparison is carried out using a digital timing measurement circuit, such as a time-to-digital converter.

The second patent is titled "Method and device for testing TSVs in a 3D chip stack." This invention discloses a method and device for testing TSVs in a 3D chip stack. The 3D chip stack includes at least a first die with a first electrical circuit and a second die with a second electrical circuit. The first die includes at least one first TSV for providing electrical connection between the two circuits. Additionally, the first die includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. This design allows for testing the first TSV in the first die even if the second die lacks dedicated test circuitry.

Career Highlights

Nikolaos Minas is currently employed at Imec, a leading research and innovation hub in nanoelectronics and digital technologies. His work at Imec has positioned him at the forefront of technological advancements in integrated circuits.

Collaborations

Throughout his career, Nikolaos has collaborated with notable colleagues, including Geert Van Der Plas and Erik-Jan Marinissen. These collaborations have further enriched his research and contributions to the field.

Conclusion

Nikolaos Minas is a distinguished inventor whose work in integrated circuits and TSV testing has made a significant impact on the industry. His innovative patents and contributions

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…