The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 26, 2013
Filed:
Sep. 27, 2010
Geert Van Der Plas, Leuven, BE;
Erik-jan Marinissen, Leuven, BE;
Nikolaos Minas, Kessel-Lo, BE;
Paul Marchal, Blanden, BE;
Geert Van der Plas, Leuven, BE;
Erik-Jan Marinissen, Leuven, BE;
Nikolaos Minas, Kessel-Lo, BE;
Paul Marchal, Blanden, BE;
IMEC, Leuven, BE;
Abstract
A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry.