San Jose, CA, United States of America

Neeladri Sain

This inventor holds 1 USPTO granted patent. Top assignee: Apple Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Neeladri Sain. Retrieved from https://idiyas.com/inventor/neeladri-sain-meas14ad

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Neeladri Sain and Power-Gated Integrated Circuit Design

Introduction

Neeladri Sain is an inventor associated with Apple Inc. in San Jose, California. His patent work addresses power management in integrated circuit devices, with a design intended to use space efficiently while providing power gating for functional circuit regions.

Latest Patents

Sain is associated with 1 patent, titled “Power Switch Design.” The patent describes integrated circuit devices with power-gated domains positioned between functional circuit regions. Power-switch cells in these domains have active-region logic that is continuous with the active-region logic in boundary cells next to the functional regions. This arrangement is designed to provide sufficient power gating while making efficient use of the space between regions. The approach may be particularly useful when the functional regions contain memory circuits.

Career Highlights

The available information connects Sain’s patent activity with Apple Inc. and highlights his work on power-switch-cell design for integrated circuits. The described invention focuses on combining power-management capability with efficient circuit layout.

Collaborations

Sain’s listed coworkers include Kapil K. Kothari and Abhimanyu Sharma. Their inclusion identifies professional associations, though the available information does not specify their roles in the patent.

Conclusion

Neeladri Sain’s patent on power-switch design describes a layout-conscious approach to power gating in integrated circuits, particularly for regions containing memory circuits.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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