logo

For the Inventor, By the Inventor

Boise, ID, United States of America

Neal L Davis

This inventor holds 6 USPTO granted patents. Top assignee: Micron Technology Incorporated. Active years: 2011-2016.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Neal L Davis. Retrieved from https://idiyas.com/inventor/neal-l-davis

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 6

% Patents Active = 100.0

Average Co-Inventor Count = 2.6

ph-index = 3

Forward Citations = 18(Granted Patents)


Company Filing History:

goldMedal6 out of 39,222 
 
Micron Technology Incorporated
 patents

Years Active: 2011-2016

Loading Chart...
6 patents (USPTO):Explore Patents
1. 9373636 - Methods of forming semiconductor constructions (2016-06-21),
2. 9178077 - Semiconductor constructions (2015-11-03),
3. 8796086 - Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate (2014-08-05),
4. 8586429 - Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate (2013-11-19),
5. 8389353 - Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate (2013-03-05),
6. 8039340 - Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate (2011-10-18),

Title: Neal L. Davis: Innovator in Semiconductor Technology

Introduction

Neal L. Davis is a prominent inventor based in Boise, ID (US), known for his significant contributions to semiconductor technology. With a total of 6 patents to his name, Davis has made remarkable advancements in the field, particularly in methods of forming semiconductor constructions.

Latest Patents

Davis's latest patents focus on innovative methods of forming semiconductor constructions. Some embodiments include a semiconductor construction featuring a stack that contains alternating levels of control gate material and intervening dielectric material. A channel material panel extends through the stack and along a first direction, dividing the stack into a first section on one side of the panel and a second section on the opposite side. Memory cell stacks are positioned between the channel material panel and the control gate material. These memory cell stacks consist of cell dielectric material shaped as containers with open ends directed toward the channel material panel, containing charge-storage material within the containers. This inventive approach enhances the efficiency and functionality of semiconductor devices.

Career Highlights

Neal L. Davis has built a successful career at Micron Technology Incorporated, where he has played a crucial role in advancing semiconductor technologies. His work has not only contributed to the company's success but has also influenced the broader field of electronics.

Collaborations

Throughout his career, Davis has collaborated with notable colleagues, including Richard T. Housley and Ranjan Khurana. These partnerships have fostered innovation and have led to the development of cutting-edge technologies in the semiconductor industry.

Conclusion

Neal L. Davis stands out as a key figure in semiconductor innovation, with a strong portfolio of patents that reflect his expertise and dedication to advancing technology. His contributions continue to shape the future of the semiconductor industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…