Location History:
- Davis, CA (US) (2002)
- Folsom, CA (US) (2005)
Company Filing History:
Years Active: 2002-2005
Title: Narayanan S Iyer: Innovator in Chip Multiprocessor Technology
Introduction
Narayanan S Iyer is a notable inventor based in Folsom, CA. He has made significant contributions to the field of chip multiprocessor technology, holding 2 patents that showcase his innovative approach to enhancing processor performance and efficiency.
Latest Patents
One of his latest patents is titled "Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system." This invention describes a multicore processor that includes multiple processor cores, each equipped with a private cache and a shared cache. An internal snoop bus connects each private cache to the shared cache, facilitating data communication among them. Another significant patent is the "Method and system for implementing control signals on a low pin count bus." This invention allows devices to communicate efficiently using a low pin count bus, which comprises a set of data lines, a strobe line, and one control line. Command information is transmitted simultaneously with data, defined by its timing.
Career Highlights
Narayanan S Iyer is currently employed at Intel Corporation, where he continues to push the boundaries of technology. His work focuses on improving the efficiency and performance of multiprocessor systems, making a lasting impact in the tech industry.
Collaborations
Throughout his career, Narayanan has collaborated with esteemed colleagues, including Vladimir M Pentkovski and Vivek Garg. These partnerships have contributed to the advancement of innovative technologies in the field.
Conclusion
Narayanan S Iyer's contributions to chip multiprocessor technology and his innovative patents reflect his dedication to advancing the field. His work at Intel Corporation continues to influence the future of processor design and efficiency.