Intel Corporation

Narayanan S Iyer

Shreekant S Thakkar

Robert J Greiner

Vivek Garg

Vladimir M Pentkovski

Jeff C Morriss

Peter J Ruscito

Pranav H Mehta

Jagannath Keshava

A method and apparatus for shared cache coherency for a chip multiprocessor or a multiprocessor system. In one embodiment, a multicore processor includes a plurality of processor cores, each having a private cache, and a shared cache. An internal snoop bus is coupled to each private cache and the shared cache to communicate data from each private cache to other private caches and the shared cache. In another embodiment, an apparatus includes a plurality of processor cores and a plurality of caches. One of the plurality of caches maintains cache lines in two different modified states. The first modified state indicates a most recent copy of a modified cache line, and the second modified state indicates a stale copy of the modified cache line.

Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system

A method and system are disclosed allowing devices to communicate using a highly efficient low pin count bus comprising a set of data lines, a strobe line, and one control line. Command information is transmitted simultaneously with data, the command information being defined by its timing.

Method and system for implementing control signals on a low pin count bus

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Folsom, CA, United States of America

Narayanan S Iyer