Okayama, Japan

Naoki Kaise

This inventor holds 1 USPTO granted patent. Top assignee: Murata Manufacturing Co., Ltd.. Active years: 2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Naoki Kaise. Retrieved from https://idiyas.com/inventor/naoki-kaise-py3uy36x

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2010

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1 patent (USPTO):Explore Patents

Title: Naoki Kaise: Innovator in Multilayer Substrate Technology

Introduction

Naoki Kaise is a prominent inventor based in Okayama, Japan. He has made significant contributions to the field of multilayer substrate technology. His innovative work has led to the development of a unique internal conductor connection structure.

Latest Patents

Naoki Kaise holds a patent for an internal conductor connection structure and multilayer substrate. This patent describes a multilayer substrate that includes an internal conductor connection structure featuring first and second via conductors positioned adjacent to each other. The first via conductor is designed to extend away from the second via conductor and connects to a first line conductor through a continuous via conductor.

Career Highlights

Kaise is associated with Murata Manufacturing Co., Ltd., a leading company in electronic components. His work at Murata has allowed him to focus on advancing multilayer substrate technology, which is crucial for modern electronic devices.

Collaborations

Some of his notable coworkers include Issey Yamamoto and Yutaka Morikita. Their collaboration has contributed to the innovative environment at Murata Manufacturing Co., Ltd.

Conclusion

Naoki Kaise's contributions to multilayer substrate technology exemplify the importance of innovation in the electronics industry. His patent reflects a significant advancement that can enhance the performance of electronic devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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