Naohito Kohashi

This inventor holds 10 USPTO granted patents. Top assignees: Fujitsu Semiconductor Limited, Fujitsu Corporation. Active years: 2004-2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Naohito Kohashi. Retrieved from https://idiyas.com/inventor/naohito-kohashi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 10

% Patents Active = 20.0

Average Co-Inventor Count = 3.9

ph-index = 3

Forward Citations = 50(Granted Patents)

Location History:

Kanagawa, JP (2010)
Kawasaki, JP (2004 - 2012)

Company Filing History:

6 out of 1,674

Fujitsu Semiconductor Limited

Years Active: 2004-2012

Loading Chart...

10 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8268670 - Method of semiconductor device protection (2012-09-18),

2. 8164181 - Semiconductor device packaging structure (2012-04-24),

3. 7977961 - Component for testing device for electronic component and testing method of the electronic component (2011-07-12),

4. 7921906 - Temperature control method and temperature control device (2011-04-12),

5. 7825676 - Contactor and test method using contactor (2010-11-02),

6. 7807481 - Method of semiconductor device protection, package of semiconductor device (2010-10-05),

7. 7471096 - Contactor for electronic parts and a contact method (2008-12-30),

8. 7382046 - Semiconductor device protection cover, and semiconductor device unit including the cover (2008-06-03),

9. 6784657 - Handling apparatus and test set using the handling apparatus (2004-08-31),

10. 6767219 - Contactor, method for manufacturing such contactor, and testing method using such contactor (2004-07-27),

Title: Naohito Kohashi: Innovator in Semiconductor Device Protection

Introduction

Naohito Kohashi is a prominent inventor based in Kawasaki, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 10 patents. His work focuses on improving the reliability and protection of semiconductor devices during various stages, including testing and transportation.

Latest Patents

Kohashi's latest patents include a method of semiconductor device protection. This innovative method enhances the reliability of performance tests for semiconductor devices and prevents damage during transportation or packaging for shipment. The invention features an IC cover that accommodates height unevenness caused by semiconductor chips and electric parts of varying heights. The IC cover consists of projecting portions and a base portion. Once attached to the semiconductor device, the projecting portions stand freely within the device, while the base portion is supported by these projections, ensuring separation from the semiconductor chips and electric parts. The IC cover is designed to be detachably attached to the semiconductor device.

Another notable patent is the semiconductor device packaging structure, which shares similar benefits as the method of protection. This structure also aims to improve reliability during performance tests and safeguard the semiconductor device from damage during transportation or packaging.

Career Highlights

Throughout his career, Naohito Kohashi has worked with esteemed companies such as Fujitsu Semiconductor Limited and Fujitsu Corporation. His experience in these organizations has allowed him to develop and refine his innovative ideas in semiconductor technology.

Collaborations

Kohashi has collaborated with notable coworkers, including Shigeyuki Maruyama and Kazuhiro Tashiro. Their combined expertise has contributed to the advancement of semiconductor device protection technologies.

Conclusion

Naohito Kohashi's contributions to semiconductor technology through his patents and collaborations highlight his role as an influential inventor in the field. His innovative methods and structures continue to enhance the reliability and safety of semiconductor devices.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]