Hillsboro, OR, United States of America

Nagaraju N Kodalapura

This inventor holds 5 USPTO granted patents. Top assignee: Intel Corporation. Active years: 2018-2023.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Nagaraju N Kodalapura. Retrieved from https://idiyas.com/inventor/nagaraju-n-kodalapura

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 80.0

Average Co-Inventor Count = 2.4

ph-index = 2

Forward Citations = 20(Granted Patents)


Company Filing History:


Years Active: 2018-2023

Loading Chart...
5 patents (USPTO):Explore Patents

Title: Innovations by Nagaraju N Kodalapura

Introduction

Nagaraju N Kodalapura is a prominent inventor based in Hillsboro, OR (US). He has made significant contributions to the field of technology, particularly in memory security. With a total of 5 patents to his name, his work focuses on preventing memory attacks and enhancing system security.

Latest Patents

One of his latest patents is titled "Techniques for preventing memory timing attacks." This patent describes techniques and apparatuses for detecting and preventing memory attacks. In one embodiment, the apparatus includes at least one memory comprising a shared memory and a system memory. The logic, which is partially comprised in hardware, is coupled to the shared memory. It implements a memory monitor to determine a memory attack by an attacker application against a victim application using the shared memory. The monitor prevents the memory attack by determining that victim data is being reloaded into the shared memory from the system memory, storing the victim data in a monitor memory, flushing shared memory data, and writing the victim data to the shared memory.

Another notable patent is the "Hardware based technique to prevent critical fine-grained cache side-channel attacks." This system includes a processor and a memory, with the processor having at least one cache. The cache consists of multiple sets, each containing several cache lines. Each cache line includes bits for storing information, including a 'shared' bit to indicate whether the cache line is shared between different processes. The cache logic monitors for context switches and evicts shared cache lines to prevent attackers from gleaning meaningful information.

Career Highlights

Nagaraju N Kodalapura is currently employed at Intel Corporation, where he continues to innovate and develop advanced security technologies. His work has been instrumental in enhancing the security of memory systems and protecting against various types of attacks.

Collaborations

He has collaborated with notable colleagues, including Arun Kanuparthi and Abhishek Basak, contributing to the advancement of technology in their field.

Conclusion

Nagaraju N Kodalapura's contributions to memory security through his innovative patents demonstrate his expertise and commitment to advancing technology. His work at Intel Corporation continues to impact the industry positively.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…