N Gopalan Nair

Title: N Gopalan Nair and Multiprocessor Memory Architecture.

Introduction

N Gopalan Nair is an inventor associated with Chandler, Arizona, and Intel Corporation. His patent work includes multiprocessor memory architectures designed to improve how processors share data and access program instructions. The supplied information lists 4 patents.

Latest Patents

“Method to Share Memory in a Single Chip Multiprocessor System” describes a system in which memory banks can be dynamically switched between processors. This arrangement allows blocks of data to be shared without physically copying them between banks. Program-memory banks can also be loaded with instruction pages and connected to either processor, supporting flexible placement and relocation of program code.

“Paged Memory Architecture for a Single Chip Multi-Processor” describes a related approach to organizing memory and instruction pages. Pages appear as a contiguous address space when connected to a shared bus, while their addressing changes when connected to a processor’s private program bus. This enables processors to execute code from available pages regardless of where the code was loaded.

Career Highlights

Nair’s listed inventions focus on memory sharing, page mapping, and relocatable program code in single-chip multiprocessor systems. These techniques address the coordination of data and instructions across processors.

Collaborations

The supplied information identifies Intel Corporation as Nair’s company and lists David R. Regenold and Ramprasad Satagopan as coworkers.

Conclusion

N Gopalan Nair’s listed patent contributions center on flexible memory architectures that help multiprocessor systems share data and access program code efficiently.