Hwaseong, South Korea

Myungnam Lee

This inventor holds 2 USPTO granted patents and 1 published patent application. Top assignee: Samsung Electronics Co., Ltd.. Active years: 2023-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Myungnam Lee. Retrieved from https://idiyas.com/inventor/myungnam-lee

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 2 

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2023-2025

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2 patents (USPTO):Explore Patents

Title: Myungnam Lee and Nonvolatile Memory Innovation.

Introduction

Myungnam Lee is an inventor based in Hwaseong, South Korea, whose patent work concerns nonvolatile memory technology. Lee is associated with Samsung Electronics Co., Ltd. and has 2 patents listed in the provided information.

Latest Patents

Lee’s listed patent, “Nonvolatile Memory Device and Method of Detecting Defective Memory Cell Block of Nonvolatile Memory Device,” describes a method for identifying defective memory blocks after an erase operation. The system reads selected memory cells using an off-cell detection voltage distinct from the usual read reference voltage, counts hard off-cells with threshold voltages above that detection level, and uses the count to determine whether the target block is defective.

Career Highlights

The available patent information highlights Lee’s work on memory reliability and defect detection. The described approach uses cell-read results and hard off-cell counts to help identify potentially defective blocks in a nonvolatile memory system.

Collaborations

Lee’s listed coworkers include Daehan Kim and Wontaeck Jung. The patent information connects their work with Samsung Electronics Co., Ltd.

Conclusion

Myungnam Lee’s listed invention focuses on detecting defective blocks in nonvolatile memory, contributing to efforts to assess memory reliability through cell-level measurements.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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