Tokyo, Japan

Mitsuhiro Toya

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Renesas Electronics Corporation. Active years: 2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mitsuhiro Toya. Retrieved from https://idiyas.com/inventor/mitsuhiro-toya

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

% Patents Active = 100.0

Average Co-Inventor Count = 7.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2012

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1 patent (USPTO):Explore Patents

Title: Mitsuhiro Toya: Semiconductor Device Innovation

Introduction

Mitsuhiro Toya is an inventor based in Tokyo, Japan, associated with Renesas Electronics Corporation. His patent work includes a semiconductor technology designed to reduce capacitor parasitic capacitance while limiting the space the capacitor occupies.

Latest Patents

Toya is listed on 1 patent: “Semiconductor Device, RF-IC and Manufacturing Method of the Same.” The invention forms a stacked structure from two capacitors that share an intermediate electrode. A step in that electrode increases the spacing between electrodes outside the capacitor formation region, while keeping the spacing smaller within the region. This arrangement is intended to reduce parasitic capacitance without requiring additional capacitor area.

Career Highlights

The available information connects Toya’s patent activity with Renesas Electronics Corporation and semiconductor device development. The patent describes a capacitor structure relevant to semiconductor devices and radio-frequency integrated circuits.

Collaborations

Toshinori Imai and Takeshi Saikawa are identified as Toya’s coworkers. The provided information does not specify their roles in the patent or establish them as co-inventors.

Conclusion

Mitsuhiro Toya’s documented patent contribution focuses on a compact capacitor structure intended to reduce parasitic capacitance in semiconductor devices and RF integrated circuits.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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