Minoru Nizaka

This inventor holds 6 USPTO granted patents. Top assignees: Nec Corporation, Nec Electronics Corporation. Active years: 1994-2004.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Minoru Nizaka. Retrieved from https://idiyas.com/inventor/minoru-nizaka

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 6

% Patents Active = 66.7

Average Co-Inventor Count = 1.6

ph-index = 3

Forward Citations = 42(Granted Patents)

Location History:

Tokyo, JP (1994 - 1997)
Kanagawa, JP (1994 - 2004)

Company Filing History:

Nec Electronics Corporation

patents

Years Active: 1994-2004

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6 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6834004 - Semiconductor integrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout (2004-12-21),

2. 6831484 - Semiconductor integrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout (2004-12-14),

3. 6545892 - Semiconductor integrated circuit having logic circuit comprising transistors with lower threshold voltage values and improved pattern layout (2003-04-08),

4. 5682389 - Non-volatile memory device having built-in test pattern generator used (1997-10-28),

5. 5325323 - Erasable and programmable ROM with an identification code (1994-06-28),

6. 5293561 - Write-in voltage source incorporated in electrically erasable (1994-03-08),

Title: Minoru Nizaka: Innovator in Semiconductor Technology

Introduction

Minoru Nizaka is a prominent inventor based in Kanagawa, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 6 patents. His work focuses on improving the efficiency and design of integrated circuits.

Latest Patents

One of Nizaka's latest patents is for a semiconductor integrated circuit that features a logic circuit comprising transistors with lower threshold voltage values and an improved pattern layout. This innovation allows for a reduction in the decoder area, which effectively decreases the overall chip size. The design includes MOS FETs, where those not supplying electric charges have lower threshold voltage values than the MOS FET responsible for charge supply. Additionally, the gate width of each MOS FET is oriented perpendicular to the direction of the word lines in the memory cell areas, ensuring all MOS FETs are aligned accordingly.

Career Highlights

Throughout his career, Minoru Nizaka has worked with notable companies such as NEC Electronics Corporation and NEC Corporation. His experience in these organizations has contributed to his expertise in semiconductor technology and innovation.

Collaborations

Nizaka has collaborated with several professionals in his field, including Susumu Takano and Tomohiro Kitano. These collaborations have likely enhanced his work and led to further advancements in semiconductor design.

Conclusion

Minoru Nizaka's contributions to semiconductor technology through his patents and collaborations highlight his role as an influential inventor. His innovative designs continue to impact the efficiency and functionality of integrated circuits.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]