The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 08, 2003

Filed:

Dec. 19, 2000
Applicant:
Inventors:

Susumu Takano, Tokyo, JP;

Hiroyuki Takahashi, Tokyo, JP;

Minoru Nizaka, Kanagawa, JP;

Tomohiro Kitano, Kanagawa, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/02 ;
U.S. Cl.
CPC ...
G11C 5/02 ;
Abstract

A semiconductor integrated circuit including a logic circuit is disclosed, in which the decoder area can be reduced and which has an effect of reduction of the whole chip size. Among the MOS FETs included in the logic circuit, those other than a MOS FET for supplying electric charges via an output terminal have threshold voltage values lower than the threshold voltage value of the MOS FET for supplying electric charges. The direction of the gate width of each MOS FET is perpendicular to the direction along which word lines extend in the memory cell areas, and all of the MOS FETs are aligned in a direction perpendicular to the direction along which the word lines extend.


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