Min-Yi Fang

Title: Min-Yi Fang: Innovator in Verification Error Handling

Introduction

Min-Yi Fang is a notable inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of verification error handling, particularly through his innovative patent. His work is essential in improving the accuracy and efficiency of verification processes in various systems.

Latest Patents

Min-Yi Fang holds a patent titled "System and methods for handling verification errors." This patent discloses systems, apparatus, and methods for addressing verification violations. The method involves storing a list of fix information alongside geometric shapes for each layer during verification, such as design rule checking. For each primitive operation step performed during verification, two tasks are executed. The first task creates fix information for each violation during dimensional checking operations and adds it to the output layer's fix information list. The second task involves passing the fix information from input layers that overlap any output shape to the output layer's fix information list. Ultimately, fix guides for the final violation results are generated based on the final fix information list.

Career Highlights

Min-Yi Fang is currently employed at Synopsys, Inc., where he continues to develop innovative solutions in the field of verification. His expertise and dedication have made him a valuable asset to the company and the industry.

Collaborations

Throughout his career, Min-Yi Fang has collaborated with esteemed colleagues, including Zhen-Min Wu and Shun-Chin Chang. These collaborations have further enhanced his work and contributed to advancements in verification technologies.

Conclusion

Min-Yi Fang's contributions to the field of verification error handling are noteworthy. His innovative patent and career at Synopsys, Inc. highlight his commitment to improving verification processes. His work continues to influence the industry positively.