SEOUL, South Korea

Min Kyoung Joo

This inventor holds 1 USPTO granted patent. Top assignee: Samsung Electronics Co., Ltd.. Active years: 2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Min Kyoung Joo. Retrieved from https://idiyas.com/inventor/min-kyoung-joo

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 7.0

ph-index = 1


Company Filing History:


Years Active: 2025

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1 patent (USPTO):Explore Patents

Title: Min Kyoung Joo: Innovator in Wafer Defect Testing

Introduction

Min Kyoung Joo is a prominent inventor based in Seoul, South Korea. He is known for his significant contributions to the field of semiconductor technology, particularly in wafer defect testing. His innovative approach has led to advancements that improve defect prediction performance and reduce simulation time.

Latest Patents

Min Kyoung Joo holds a patent for a "Wafer defect test apparatus, wafer defect test system, wafer test method and fabrication method of a wafer." This invention includes a wafer variable generator that processes structural measurement data and process condition data from multiple wafers. It generates various process variables and calculates an abnormal wafer index to predict defects effectively. The technology aims to enhance the efficiency and accuracy of wafer testing.

Career Highlights

Min Kyoung Joo is currently employed at Samsung Electronics Co., Ltd., a leading company in the electronics industry. His work focuses on developing advanced testing methodologies that are crucial for maintaining the quality of semiconductor products. His expertise in this area has made him a valuable asset to his team.

Collaborations

Min Kyoung Joo collaborates with talented colleagues, including Sung Hee Lee and Jae Yoon Kim. Together, they work on innovative projects that push the boundaries of semiconductor technology.

Conclusion

Min Kyoung Joo's contributions to wafer defect testing exemplify the importance of innovation in the semiconductor industry. His work not only enhances testing methodologies but also plays a crucial role in ensuring the quality of electronic devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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