Yunlin, Taiwan

Min-Hsuan Chung

This inventor holds 2 USPTO granted patents. Top assignee: Anaglobe Technology, Inc.. Active years: 2025-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Min-Hsuan Chung. Retrieved from https://idiyas.com/inventor/min-hsuan-chung

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1


Company Filing History:


Years Active: 2025-2026

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2 patents (USPTO):Explore Patents

Title: Min-Hsuan Chung: Innovator in Warpage-Aware Floorplanning

Introduction

Min-Hsuan Chung is a notable inventor based in Yunlin County, Taiwan. He has made significant contributions to the field of heterogeneous integration structures through his innovative methods. His work focuses on optimizing floorplanning techniques to address warpage issues in integrated circuits.

Latest Patents

Min-Hsuan Chung holds a patent for a "Method of warpage-aware floorplanning for heterogeneous integration structure." This method, executed by a computer, involves several steps. It begins with layout partitioning to divide a layout into multiple grids. Following this, an initial floorplanning is performed to establish geometric relations between various dies. The process continues with global floorplanning to optimize the warpage effect, and concludes with detailed floorplanning to determine the order of die placement based on material differences.

Career Highlights

Chung is currently employed at Anaglobe Technology, Inc., where he applies his expertise in developing advanced integration techniques. His innovative approach has positioned him as a key figure in his field, contributing to the advancement of technology in heterogeneous integration.

Collaborations

He collaborates with talented coworkers, including Yang Hsu and Yao-Wen Chang, who share his commitment to innovation and excellence in technology.

Conclusion

Min-Hsuan Chung's contributions to warpage-aware floorplanning highlight his role as a leading inventor in the field of heterogeneous integration. His innovative methods continue to influence advancements in technology and improve the efficiency of integrated circuits.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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