Min-Hsiang Chiang

Title: Min-Hsiang Chiang and Semiconductor Capacitor Innovation.

Introduction

Min-Hsiang Chiang is an inventor associated with Taiwan Semiconductor Manufacturing Company Ltd. His patent work addresses a semiconductor fabrication challenge: preventing unwanted conductive residue that can cause leakage or electrical shorts.

Latest Patents

Chiang is credited with 1 patent, titled “Approach for Forming a Buried Stack Capacitor Structure Featuring Reduced Polysilicon Stringers.” The invention describes a process for forming a buried stack capacitor in a recessed region of a shallow trench isolation structure. It uses a silicon oxide layer, photoresist plugs, and a wet-etch sequence to define the polysilicon storage node while protecting the intended structure. The process is designed to reduce polysilicon stringers or residuals that could create leakage paths or shorts between conductive elements.

Career Highlights

Chiang’s listed patent work is connected to semiconductor manufacturing at Taiwan Semiconductor Manufacturing Company Ltd. The invention focuses on improving the reliability of capacitor fabrication through careful control of material protection and etching steps.

Collaborations

The provided information lists Chen-Jong Wang and Chi-Hsing Lo as Chiang’s coworkers. Their specific roles in the patent or related work are not specified.

Conclusion

Min-Hsiang Chiang’s patent highlights a fabrication approach intended to reduce unwanted polysilicon residue and improve the reliability of buried stack capacitor structures.