Milind G Weiling

Title: Milind G. Weiling and Semiconductor Planarization Innovation.

Introduction

Milind G. Weiling is an inventor associated with San Jose, California. His patent work addresses planarization in sub-micron and deep sub-micron semiconductor devices, with a focus on improving etch-back control, reliability, and protection of underlying metal traces.

Latest Patents

The available information identifies one patent for Weiling: “Method Enhancing Planarization Etchback Margin, Reliability, and Void-Free Planarization of Sub-Micron and Deep Sub-Micron Semiconductor Devices.” The method adds a silicon-enriched oxide layer over a conventionally fabricated device and its metal traces, followed by conventional TEOS-based oxide and spin-on glass layers.

The silicon-enriched oxide serves as a buffer during etch-back. Its etch rate is about 75% of the rate for stoichiometric TEOS-based oxide, helping slow the process as it approaches the metal traces and reducing the risk of exposing them. Because the layer is relatively deficient in oxygen, it releases fewer oxygen atoms during etching and does not greatly accelerate the spin-on glass etch rate.

The patent also describes a protective effect on the underlying device. The silicon-enriched oxide can neutralize charges that might otherwise influence the semiconductor, and the described approach can extend hot-carrier lifetime by about an order of magnitude. The patent specifies an index of refraction of at least about 1.50, a dangling-bond density of about 10¹⁷ per cubic centimeter, and a typical thickness of 1,000 to 2,000 angstroms.

Career Highlights

Weiling’s documented patent contribution combines process control with device reliability considerations. The invention uses material properties to improve planarization margins while helping protect metal traces and the semiconductor beneath them. The supplied information does not identify an employer, so no company affiliation is included.

Collaborations

Vivek Jain and Dipankar Pramanik are identified as Weiling’s coworkers. The available information does not specify their roles in the patent or the nature of their collaboration.

Conclusion

Milind G. Weiling’s identified patent presents a silicon-enriched oxide layer as a practical way to improve semiconductor planarization control while supporting device protection and reliability.