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San Jose, CA, United States of America

Miles P McGowan

This inventor holds 6 USPTO granted patents and 1 published patent application. Top assignee: Cadence Design Systems, Inc.. Active years: 2013-2015.

USPTO Granted Patents = 6 (Patent Applications = 1)

Average Co-Inventor Count = 2.3

ph-index = 2

Forward Citations = 15(Granted Patents)

Location History:

Campbell, CA (US) (2013)
San Jose, CA (US) (2013 - 2015)

Company Filing History:

Cadence Design Systems, Inc.

Years Active: 2013-2015

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6 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 9135373 - Method and system for implementing an interface for I/O rings (2015-09-15),

2. 8683412 - Method and system for optimizing placement of I/O element nodes of an I/O ring for an electronic design (2014-03-25),

3. 8516433 - Method and system for mapping memory when selecting an electronic product (2013-08-20),

4. 8443323 - Method and system for implementing a structure to implement I/O rings and die area estimations (2013-05-14),

5. 8386981 - Method and systems for implementing I/O rings and die area estimations (2013-02-26),

6. 8375344 - Method and system for determining configurations (2013-02-12),

Profile summary based on public USPTO records.

Please report any incorrect information to [email protected]

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