Chita, Japan

Mikiya Tadaki

This inventor holds 1 USPTO granted patent. Top assignee: Ngk Insulators, Inc.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mikiya Tadaki. Retrieved from https://idiyas.com/inventor/mikiya-tadaki-jjbvd9cd

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Mikiya Tadaki - Innovator in Wafer Placement Technology.

Introduction

Mikiya Tadaki is a notable inventor based in Chita, Japan. He has made significant contributions to the field of semiconductor technology, particularly with his innovative designs in wafer placement systems. His work is characterized by a focus on enhancing the efficiency and functionality of wafer handling processes.

Latest Patents

Mikiya Tadaki holds a patent for a wafer placement table. This invention includes a conductor unit that features a sub-RF electrode and a jumper layer embedded at different levels within a ceramic substrate. The design ensures electrical continuity between these layers, utilizing a transversely placed coil or a perforated cylindrical body as the conductor unit. This innovation is crucial for improving the precision and reliability of wafer placement in semiconductor manufacturing.

Career Highlights

Mikiya Tadaki is currently employed at NGK Insulators, Inc., where he continues to develop cutting-edge technologies in the semiconductor industry. His expertise and innovative mindset have positioned him as a valuable asset to his company and the broader field of electronics.

Collaborations

Mikiya collaborates with Takuya Yokono, a fellow innovator, to further enhance their research and development efforts. Their partnership exemplifies the importance of teamwork in driving technological advancements.

Conclusion

Mikiya Tadaki's contributions to wafer placement technology reflect his dedication to innovation and excellence in the semiconductor industry. His patent for the wafer placement table showcases his ability to solve complex engineering challenges.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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