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Groebenzell, Germany

Michael Scheppler

This inventor holds 6 USPTO granted patents and 1 published patent application. Top assignee: Infineon Technologies Ag. Active years: 2007-2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Michael Scheppler. Retrieved from https://idiyas.com/inventor/michael-scheppler

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 6 (Patent Applications = 1)

% Patents Active = 16.7

Average Co-Inventor Count = 2.5

ph-index = 4

Forward Citations = 179(Granted Patents)

Location History:

Grobenzell, DE (2007)
Gröbenzell, DE (2008 - 2010)

Company Filing History:

6 out of 15,040

Infineon Technologies Ag

Years Active: 2007-2010

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6 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 7755110 - Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zone (2010-07-13),

2. 7492187 - Circuit arrangement for supplying configuration data in FPGA devices (2009-02-17),

3. 7439765 - Mask-programmable logic macro and method for programming a logic macro (2008-10-21),

4. 7348795 - Configurable logic component without a local configuration memory and with a parallel configuration bus (2008-03-25),

5. 7323904 - Look-up table (2008-01-29),

6. 7199618 - Logic circuit arrangement (2007-04-03),

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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