Infineon Technologies Ag

Michael Scheppler

Winfried Kamp

Siegmar Koeppe

Jörg Gliese

Siegmar Köppe

Wolfgang Gruber

Francisco-Javier Veredas-Ramirez

An integrated semiconductor circuit has a regular array of logic function blocks (L) and a regular array of wiring zones (X) corresponding thereto. The wiring lines in at least one wiring layer of a wiring zone (X) are realized as line segments that are continuous within the wiring zone and are interrupted at zone boundaries. Furthermore, the semiconductor circuit comprises driver cells that surround a logic cell of the logic function block in an L-shaped manner.

Architecture of function blocks and wirings in a structured ASIC and configurable driver cell of a logic cell zone

A circuit arrangement for supplying configuration data in an FPGA device includes a plurality of output flip flops allocated to respective configurable logic cells of the FGPGA device. Each output flip flop comprises at least one data input and one data output and a data input of a first output flip flop of the plurality of output flip flops is switchably connected to a data output of a second output flip flop of the plurality of output flip flops for forming a shift register by means of a switching device integrated in the FPGA device.

Circuit arrangement for supplying configuration data in FPGA devices

A mask-programmable logic macro includes at least three input terminals an output terminal and a first set of transistors comprised of at least three transistors formed on a semiconductor substrate, each of the transistors comprising a controllable path and a control terminal. The controllable paths can be connected in series with one another between a first supply terminal and the output terminal by metallizing first metallization regions. The the transistors of the first set of transistors are arranged on the semiconductor substrate in such a way that at least one controllable path of the transistors can be bridged by metallizing one of the first metallization regions. A respective of the input terminals can be connected to a respective of the control terminals by metallizing a second metallization region.

Mask-programmable logic macro and method for programming a logic macro

A configurable logic component () does not have a local configuration memory. The configuration of the configurable logic component is defined by applied voltages. The configuration voltages are advantageously generated in an external configuration memory (). In one preferred refinement, a memory chip () (for example EEPROM) and the inventive logic component without a configuration memory () are mounted face-to-face. An intermediate, structured solder layer () makes available a plurality of electrical connections.

Configurable logic component without a local configuration memory and with a parallel configuration bus

A read out device for reading out a data word from a memory cell is described. The read out device has memory cells, inputs for input variables for selecting a memory cell and a hierarchical arrangement of multiplexers having N hierarchical levels. The control inputs of the multiplexers of a hierarchical level are connected to an input, the inputs of the hierarchical arrangement of multiplexers are connected to the outputs of the memory cells and the number of memory cells is less than 2.

Look-up table

A logic circuit arrangement including at least two data signal inputs, at which at least two data signals are provided, a first signal path coupled to the data signal inputs, and having a plurality of transistors of a first conduction type, and a plurality of control inputs coupled to the transistors.

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Gröbenzell, Germany

Michael Scheppler