Burghausen, Germany

Michael Kloesler

This inventor holds 1 USPTO granted patent. Top assignee: Siltronic Ag. Active years: 2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Michael Kloesler. Retrieved from https://idiyas.com/inventor/michael-kloesler

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 4.0

ph-index = 1


Company Filing History:


Years Active: 2013

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1 patent (USPTO):Explore Patents

Title: Michael Kloesler and Semiconductor Wafer Thermal Processing

Introduction

Michael Kloesler is an inventor associated with Siltronic AG and based in Burghausen, Germany. His patent work addresses the support of monocrystalline silicon wafers during thermal treatment.

Latest Patents

Kloesler is associated with 1 patent: “Support ring for supporting a semiconductor wafer composed of monocrystalline silicon during a thermal treatment, method for the thermal treatment of such a semiconductor wafer, and thermally treated semiconductor wafer composed of monocrystalline silicon.”

The invention describes a support ring with a curved surface on which the wafer rests. For 300 mm wafers, the surface has a radius of curvature from 6,000 to 9,000 mm; for 450 mm wafers, the range is 9,000 to 14,000 mm. Using the support ring during thermal treatment is intended to reduce slip and improve wafer nanotopography.

Career Highlights

Kloesler’s listed patent work concerns semiconductor manufacturing, particularly wafer support and thermal processing. The patent connects the support ring’s geometry with the goal of improving the quality of thermally treated silicon wafers.

Collaborations

The supplied information identifies Thomas Loch and Raimund Kaiss as Kloesler’s coworkers. It does not specify their roles in the patent or the extent of their collaboration.

Conclusion

Michael Kloesler’s patent focuses on a carefully shaped support ring designed to reduce slip and improve nanotopography during the thermal treatment of monocrystalline silicon wafers.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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